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82575EB Gigabit Ethernet Controller — Content
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
4 January 2011
Content
1.0 Introduction ...........................................................................................................................19
1.1 Register and Bit References ........................................................................................................ 19
1.2 Byte and Bit Designations ........................................................................................................... 19
1.3 References ............................................................................................................................... 19
1.4 Memory Alignment Terminology .................................................................................................. 20
2.0 Architectural Overview ...........................................................................................................21
2.1 External Architecture ................................................................................................................. 21
2.1.1 Integrated 10/100/1000 Mb/s PHY......................................................................................... 22
2.1.2 System Interface................................................................................................................. 22
2.1.3 EEPROM Interface ............................................................................................................... 22
2.1.4 Flash Memory Interface........................................................................................................ 23
2.1.5 Management Interfaces........................................................................................................ 23
2.1.5.1 Software Watchdog ....................................................................................................... 23
2.1.6 General-Purpose I/O (Software-Definable Pins) ....................................................................... 23
2.1.7 LEDs.................................................................................................................................. 24
2.1.8 Network Interfaces .............................................................................................................. 24
2.2 DMA Addressing ........................................................................................................................ 24
2.3 Ethernet Addressing................................................................................................................... 25
2.4 Interrupt Control and Tuning....................................................................................................... 26
2.5 Hardware Acceleration Capability ................................................................................................. 26
2.5.1 Jumbo Frame Support.......................................................................................................... 27
2.5.2 Receive and Transmit Checksum Offloading ............................................................................ 27
2.5.3 TCP Segmentation............................................................................................................... 27
2.5.4 Receive Fragmented UDP Checksum Offloading ....................................................................... 27
2.6 Buffer and Descriptor Structure ................................................................................................... 27
2.7 Multiple Transmit Queues ........................................................................................................... 28
2.8 iSCSI Boot................................................................................................................................ 28
3.0 General Initialization and Reset Operation..............................................................................29
3.1 Power Up State ......................................................................................................................... 29
3.2 Initialization Sequence ............................................................................................................... 29
3.3 Interrupts During Initialization..................................................................................................... 29
3.4 Global Reset and General Configuration ........................................................................................ 30
3.5 Receive Initialization .................................................................................................................. 30
3.5.1 Initialize the Receive Control Register ....................................................................................31
3.5.2 Dynamic Queue Enabling and Disabling .................................................................................. 31
3.6 Transmit Initialization ................................................................................................................ 31
3.6.1 Dynamic Queue Enabling and Disabling .................................................................................. 32
3.7 Link Setup Mechanisms and Control/Status Bit Summary ................................................................ 32
3.7.1 PHY Initialization ................................................................................................................. 32
3.7.2 MAC/PHY Link Setup (CTRL_EXT.LINK_MODE = 00b) ............................................................... 32
3.7.3 MAC/SerDes Link Setup (CTRL_EXT.LINK_MODE = 11b)........................................................... 34
3.7.4 MAC/SGMII Link Setup (CTRL_EXT.LINK_MODE = 10b) ............................................................ 35
3.8 Reset Operation ........................................................................................................................ 37
3.8.1 PHY Behavior During a Manageability Session: ........................................................................ 41
3.9 Initialization of Statistics ............................................................................................................ 42
4.0 EEPROM and Flash Interface...................................................................................................43
4.1 EEPROM Device ......................................................................................................................... 43
4.1.1 Software Accesses............................................................................................................... 43
4.1.2 Signature and CRC Fields ..................................................................................................... 44
4.1.3 EEPROM Recovery ............................................................................................................... 44
4.1.4 Protected EEPROM Space...................................................................................................... 45
4.1.5 Initial EEPROM Programming ................................................................................................ 45
4.1.6 Activating the Protection Mechanism ...................................................................................... 46
4.1.7 Non Permitted Accesses to Protected Areas in the EEPROM ....................................................... 46
4.1.8 EEPROM-Less Support.......................................................................................................... 46