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Intel
®
82575EB Gigabit Ethernet Controller — 100 Mb/s Operation
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
274 January 2011
The descrambler requires approximately 15 s. to lock, normally accomplished during the training
phase.
11.8.3.7 Viterbi Decoder/Decision Feedback Equalizer (DFE)
The Viterbi decoder generates clean 4DPAM5 symbols from the output of the DSP. The decoder includes
a Trellis encoder identical to the one used by the transmitter. The Viterbi decoder simultaneously looks
at the received data over several baud periods. For each baud period, it predicts whether the symbol
received should be even or odd, and compares that to the actual symbol received. The 4DPAM5 code is
organized in such a way that a single level error on any channel changes an even code to an odd one
and vice versa. In this way, the Viterbi decoder can detect single-level coding errors, effectively
improving the Signal-To-Noise (SNR). When an error occurs, this information is quickly fed back into
the equalizer to prevent future errors.
11.8.3.8 4DPAM5 Decoder
The 4DPAM5 decoder generates 8B data from the output of the Viterbi decoder.
11.9 100 Mb/s Operation
The MAC passes data to the PHY over the MII. The PHY encodes and scrambles the data, then transmits
it using MLT-3 for 100TX over copper. The PHY descrambles and decodes MLT-3 data received from the
network. When the MAC is not actively transmitting data, the PHY sends out idle symbols on the line.
11.10 10 Mb/s Operation
The PHY operates as a standard 10 Mb/s transceiver. Data transmitted by the MAC as 4-bit nibbles is
serialized, Manchester-encoded, and transmitted on the MDI[0]+/- outputs. Received data is decoded,
de-serialized into 4-bit nibbles and passed to the MAC across the internal MII. The PHY supports all the
standard 10 Mb/s functions.
11.10.1 Link Test
In 10 Mb/s mode, the PHY always transmits link pulses. If the Link Test Function is enabled, it monitors
the connection for link pulses. Once it detects 2 to 7 link pulses, data transmission is enabled and
remains enabled as long as the link pulses or data reception continues. If the link pulses stop, the data
transmission is disabled.
If the Link Test function is disabled, the PHY might transmit packets regardless of detected link pulses.
Setting PHY register 16d, bit 14 can disable the Link Test function.