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82575EB Gigabit Ethernet Controller — Transmit Descriptor Write Back Format
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
138 January 2011
Table 37. Transmit Command (TDESC.CMD) Layout
Note: When tail write-back is enabled, the descriptor write-back is not executed.
7 6 5 4 3 2 1 0
RSV VLE DEXT RSV RS IC IFCS EOP
TDESC.CMD Description
Reserved (bit 7) Reserved.
VLE (bit 6) VLAN Packet Enable
Indicates that the packet is a VLAN packet (for example, hardware should add the VLAN Ether type and an
802.1q VLAN tag to the packet).
When set to 0b, sends generic Ethernet packet.
When set to 1b, sends 802.1Q packet; the Ethernet Type field comes from the VET register and the VLAN
data comes from the special field of the TX descriptor.
Note: If the VLE bit is set, the CTRL.VME bit should also be set to enable VLAN tag insertion. If the
CTRL.VME bit is not set, the 82575 does not insert VLAN tags on outgoing packets.
DEXT (bit 5) Extension (0b for legacy mode).
Should be written with 0b for future compatibility.
RSV (bit 4) Reserved
Should be programmed to 0b.
RS (bit 3) Report Status
Signals hardware to report the status information. This is used by software that does in-memory checks of
the transmit descriptors to determine which ones are done. For example, if software queues up 10 packets
to transmit, it can set the RS bit in the last descriptor of the last packet. If software maintains a list of
descriptors with the RS bit set, it can look at them to determine if all packets up to (and including) the one
with the RS bit set have been buffered in the output FIFO. Looking at the status byte and checking the
Descriptor Done (DD) bit do this. If DD is set, the descriptor has been processed.
IC (bit 2) Insert Checksum
When set, the 82575 needs to insert a checksum at the offset indicated by the CSO field. The checksum
calculations are performed for the entire packet starting at the byte indicated by the CCS field. IC is ignored
if CSO and CCS are out of the packet range. This occurs when (CSS length) or (CSO length - 1). IC is
valid only when EOP is set.
IFCS (bit 1) Insert FCS
When set, hardware appends the MAC FCS at the end of the packet. When cleared, software should
calculate the FCS for proper CRC check. There are several cases in which software must set IFCS:
Transmission of short packet while padding is enabled by the TCTL.PSP bit
Checksum offload is enabled by the IC bit in the TDESC.CMD
VLAN header insertion enabled by the VLE bit in the TDESC.CMD
EOP (bit 0) End Of Packet
When set, indicates the last descriptor making up the packet. One or many descriptors can be used to form
a packet.