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Intel
®
82575EB Gigabit Ethernet Controller — Receive Address Low - RAL (05400h + 8*n
[n=0..15]; R/W)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
380 January 2011
14.5.2 Receive Address Low - RAL (05400h + 8*n
[n=0..15]; R/W)
Note: "n" is the exact unicast/multicast address entry and it is equals to 0,1,…15.
These registers contain the lower bits of the 48 bit Ethernet address. All 32 bits are valid.
These registers are reset by a software reset or platform reset. If an EEPROM is present, the first
register (RAL0) is loaded from the EEPROM after a software or platform reset.
Note: The RAL field should be written in network order.
14.5.3 Receive Address High - RAH (05404h + 8n
[n=0..15]; R/W)
"n" is the exact unicast/multicast address entry and it is equals to 0,1,…15.
These registers contain the upper bits of the 48 bit Ethernet address. The complete address is [RAH,
RAL]. AV determines whether this address is compared against the incoming packet and is cleared by a
master reset.
ASEL enables the 82575 to perform special filtering on receive packets.
After reset, if an EEPROM is present, the first register (Receive Address Register 0) is loaded from the
IA field in the EEPROM with its Address Select field set to 00b and its Address Valid field set to 1b. If no
EEPROM is present, the Address Valid field is set to 0b and the Address Valid field for all of the other
registers is set to 0b.
Note: The RAH field should be written in network order.
The first receive address register (RAH0) is also used for exact match pause frame checking (DA
matches the first register). As a result, RAH0 should always be used to store the individual Ethernet
MAC address of the 82575.
Field Bit(s)
Initial
Value
Description
RAL 31:0 X Receive address low
Contains the lower 32-bit of the 48-bit Ethernet address.