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Receive Descriptor Write-Back — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 117
When the number of descriptors in host memory is greater than the available on-chip descriptor
storage, the 82575 might elect to perform a fetch that is not a multiple of cache line size. The hardware
performs this non-aligned fetch if doing so results in the next descriptor fetch being aligned on a cache
line boundary. This enables the descriptor fetch mechanism to be most efficient in the cases where it
has fallen behind software.
All fetch decisions are based on the number of available descriptors and do not take into account any
split of the transaction due to bus access limitations.
Note: The 82575 never fetches descriptors beyond the descriptor TAIL pointer.
5.3.7 Receive Descriptor Write-Back
Processors have cache line sizes that are larger than the receive descriptor size (16 bytes).
Consequently, writing back descriptor information for each received packet causes expensive partial
cache line updates. A Receive descriptor packing mechanism minimizes the occurrence of partial line
write backs.
5.3.7.1 Receive Descriptor Packing
To maximize memory efficiency, receive descriptors are packed together and written as a cache line
whenever possible. Descriptor write backs accumulate and are opportunistically written out in cache
line-oriented chunks as follows:
• RXDCTL.WTHRESH descriptors have been used (the specified max threshold of unwritten used
descriptors has been reached)
• The receive timer expires (EITR). In this case all descriptors are flushed ignoring any cache line
boundaries
• Explicit software flush (RXDCTLn.SWFLS)
• Dynamic packets. If at least one of the descriptors waiting for write-back is classified as a packet
requiring immediate notification, the entire queue is flushed.
When the numbers of descriptors specified by RXDCTL.WTHRESH have been used, they are written
back, regardless of cache line alignment. It is recommended that WTHRESH be a multiple of cache line
size. When the receive timer (EITR) expires, all used descriptors are forced to be written back prior to
initiating the interrupt, for consistency. Software can explicitly flush accumulated descriptors by writing
the RXDCTLn register with the SWFLS bit set.
When the 82575 does a partial cache line write-back, it attempts to recover to cache-line alignment on
the next write-back.
All write back decisions are based on the number of descriptors available and do not take into account
any split of the transaction due to bus access limitations.
5.3.8 Receive Descriptor Ring Structure
Figure 3 shows the structure of each of the four receive descriptor rings. Hardware maintains four
circular queues of descriptors and writes back used descriptors just prior to advancing the head
pointer(s). Head and tail pointers wrap back to base when size descriptors have been processed.