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Intel
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82575EB Gigabit Ethernet Controller — Initialization of Statistics
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
42 January 2011
The Keep_PHY_Link_Up bit is set by the BMC through a command on the sideband interface. It is
cleared by the external BMC (again, through a command on the sideband interface) when the
manageability session ends. Once the Keep_PHY_Link_Up bit is cleared, the PHY updates its Dx state
and acts accordingly (negotiates its speed).
The Keep_PHY_Link_Up bit is also cleared on de-assertion of the MAIN_PWR_OK input pin.
MAIN_PWR_OK must be de-asserted at least 1 ms before power drops below its 90% value. This allows
enough time to respond before auxiliary power takes over.
The Keep_PHY_Link_Up bit is a R/W bit and can be accessed by host software, but software is not
expected to clear the bit. The bit is cleared in the following cases:
• On Internal_Power_On_Reset
• When the BMC resets or initializes it
• On de-assertion of the MAIN_PWR_OK input pin. The BMC should set the bit again if it wishes to
maintain speed on exit from Dr state.
3.9 Initialization of Statistics
Statistics registers are hardware-initialized to values as detailed in each particular register’s
description. The initialization of these registers begins upon transition to D0active power state (when
internal registers become accessible, as enabled by setting the Memory Access Enable of the PCIe*
Command register) and is guaranteed to complete within 1 μs of this transition. Access to statistics
registers prior to this interval might return indeterminate values.
All of the statistical counters are cleared on read and a typical software device driver reads them
(making them zero) as a part of the initialization sequence.
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