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82575EB Gigabit Ethernet Controller — Memory Alignment Terminology
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
20 January 2011
• PCI Express* Card Electromechanical Specification, Rev 1.1RD, November 2004
• PICMG3.1 Ethernet/Fiber Channel Over PICMG 3.0 Draft Specification, September 4, 2002, Version
0.90.
• Advanced Configuration and Power Interface Specification, Rev 2.0b, October 2002
• PCI Bus Power Management Interface Specification, Rev. 1.2, March 2004
• PCI Local Bus Specification Revision 2.3 MSI-X ECN
1.4 Memory Alignment Terminology
Some 82575 data structures have special memory alignment requirements. This implies that the
starting physical address of a data structure must be aligned as specified in this manual. The following
terms are used for this purpose:
• BYTE alignment: Implies that the physical addresses can be odd or even. Examples: 0FECBD9A1h,
02345ADC6h.
• WORD alignment: Implies that physical addresses must be aligned on even boundaries. For
example, the last nibble of the address can only end in 0, 2, 4, 6, 8, Ah, Ch, or Eh (0FECBD9A2h).
• DWORD (Double-Word) alignment: Implies that the physical addresses can only be aligned on 4-
byte boundaries. For example, the last nibble of the address can only end in 0, 4, 8, or Ch
(0FECBD9A8h).
• QWORD (Quad-Word) alignment: Implies that the physical addresses can only be aligned on 8-
byte boundaries. For example, the last nibble of the address can only end in 0 or 8 (0FECBD9A8h).
• PARAGRAPH alignment: Implies that the physical addresses can only be aligned on 16-byte
boundaries. For example, the last nibble must be a 0 (02345ADC0h).
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