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Protected EEPROM Space — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 45
This mechanism uses an SMBus message that the firmware is able to receive in all modes, no matter
what the content of the EEPROM is (even in diagnostic mode). After receiving this kind of message, the
firmware clears the signature of the EEPROM in word 12h bit 15/14 to 00b. Afterwards, the BIOS/
operating system initiates a reset to force an EEPROM auto-load process that fails and enables access
to the 82575.
Firmware is programmed to receive such a command only from a PCIe* reset until one of the functions
changes it status from D0u to D0a. Once one of the functions switches to D0a, it can be safely assumed
that the 82575 is accessible to the host and there is no more need for this function. This reduces the
possibility of malicious software to use this command as a back door and limits the time the firmware
must be active in non-manageability mode.
If the firmware is programmed not to do any other function apart from answering to this command, it
can request clock gating immediately after one of the functions changes it status from D0u to D0a. If
the system goes back down to D0u from D0a, it is undefined whether firmware supports the EEPROM
recovery command.
The Command is sent on a fixed SMBus address of C8h. The format of the command is SMBus Write
Data Byte as follows:
Note: This solution requires a controllable SMBus connection to the 82575.
If more than one 82575 is in a state to accept this solution, then all the 82575s on the
board ACKs this command and accepts it. An 82575 supporting this mode should not ACK
this command if it is not in D0u state.
The 82575 is guaranteed to accept the command on the SMBus interface and on address
C8h; however, it might be accepted on other configured interfaces and addresses as well.
After receiving a release EEPROM command, firmware should keep its current state. It is the
responsibility of the programmer updating the EEPROM to send a firmware reset, if required, after the
full EEPROM update process completes.
4.1.4 Protected EEPROM Space
The 82575 provides to the host a mechanism for a hidden area in the EEPROM. The hidden area cannot
be accessed via the EEPROM registers in the CSR space. It can be accessed only by the Manageability
(MNG) subsystem. For more information on the MNG subsystem, refer to the 82575 TCO/System
Manageability Interface Application Note.
A mechanism to protect part of the EEPROM from host writes is also provided. This mechanism is
controlled by words 2Dh and 2Ch. These words control the start and the end of the read only area.
4.1.5 Initial EEPROM Programming
In most applications, initial EEPROM programming is done directly on the EEPROM pins. Nevertheless, it
is desirable to enable existing software utilities (accessing the EEPROM via the host interface) to initially
program the whole EEPROM without breaking the protection mechanism. Following a power-up
Function Command Data Byte
Release EEPROM C7h AAh