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Content — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 9
5.13.8 Extended Interrupt Mask Set and Read Register (EIMS)/Extended Interrupt Mask Clear Register (EIMC)
164
5.13.9 Extended Interrupt Auto Clear Enable Register (EIAC).............................................................164
5.13.10 Extended Interrupt Auto Mask Enable Register (EIAM).............................................................164
5.13.11 Interrupt Modes Setting Bits ................................................................................................165
5.14 Interrupt Moderation................................................................................................................ 165
5.15 Clearing Interrupt Causes ......................................................................................................... 168
5.15.1 Auto-Clear.........................................................................................................................168
5.15.2 Write to Clear ....................................................................................................................169
5.15.3 Read to Clear.....................................................................................................................169
5.16 Dynamic Interrupt Moderation................................................................................................... 169
5.16.1 TCP Timer Interrupt............................................................................................................170
5.17 Memory Error Correction and Detection ...................................................................................... 170
6.0 PCIe* Local Bus Interface..................................................................................................... 173
6.1 General Functionality ............................................................................................................... 173
6.1.1 Message Handling (Receive Side) .........................................................................................173
6.1.2 Message Handling (Transmit Side)........................................................................................173
6.1.3 Data Alignment..................................................................................................................174
6.1.3.1 4 KB Boundary ............................................................................................................174
6.1.4 Transaction Attributes.........................................................................................................174
6.1.4.1 Traffic Class and Virtual Channels...................................................................................174
6.1.4.2 Relaxed Ordering .........................................................................................................175
6.1.4.3 Snoop Not Required .....................................................................................................175
6.1.4.3.1 No Snoop and Relaxed Ordering for LAN Traffic.............................................................175
6.1.4.3.2 No Snoop Option for Payload ......................................................................................175
6.2 Flow Control ........................................................................................................................... 176
6.2.1 Flow Control Rules..............................................................................................................176
6.2.2 Upstream Flow Control Tracking ...........................................................................................176
6.2.3 Flow Control Update Frequency ............................................................................................177
6.2.4 Flow Control Timeout Mechanism..........................................................................................177
6.2.5 Error Forwarding ................................................................................................................177
6.3 Host Interface......................................................................................................................... 177
6.3.1 Tag IDs.............................................................................................................................177
6.3.2 Completion Timeout Mechanism ...........................................................................................181
6.4 Error Events and Error Reporting ............................................................................................... 182
6.4.1 Error Events ......................................................................................................................182
6.4.2 Error Pollution....................................................................................................................184
6.4.3 Unsuccessful Completion Status ..........................................................................................184
6.4.4 Error Reporting Changes .....................................................................................................184
6.5 Link Layer .............................................................................................................................. 185
6.5.1 ACK/NAK Scheme...............................................................................................................185
6.5.2 Supported DLLPs................................................................................................................185
6.5.3 Transmit EDB Nullifying.......................................................................................................186
6.6 Physical Layer ......................................................................................................................... 186
6.6.1 Link Width.........................................................................................................................186
6.6.1.1 Polarity Inversion.........................................................................................................187
6.6.1.2 L0s Exit latency ...........................................................................................................187
6.6.1.3 Lane-to-Lane De-Skew .................................................................................................187
6.6.1.4 Lane Reversal..............................................................................................................187
6.6.1.5 Reset .........................................................................................................................188
6.6.1.6 Scrambler Disable........................................................................................................188
6.6.2 Performance Monitoring ......................................................................................................188
6.6.3 Configuration Registers .......................................................................................................188
6.6.3.1 PCI Compatibility .........................................................................................................188
6.6.4 Mandatory PCI Configuration Registers..................................................................................189
6.6.5 PCI Power Management Registers.........................................................................................195
6.6.5.1 Message Signaled Interrupt (MSI) Configuration Registers.................................................197
6.6.5.2 MSI-X Configuration .....................................................................................................198
6.6.5.3 PCIe* Configuration Registers........................................................................................201
6.6.5.3.1 PCIe* Extended Configuration Space ...........................................................................210