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Intel
®
82575EB Gigabit Ethernet Controller — Packet Generator Source Address Low - PGSAL
(04288h; R/W)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
442 January 2011
14.11.3 Packet Generator Source Address Low - PGSAL
(04288h; R/W)
14.11.4 Packet Generator Source Address High - PGSAH
(0428Ch; R/W)
14.11.5 Packet Generator Inter Packet Gap - PGIPG
(04290h; R/W)
The actual gap between consecutive packets is a random value between min IPG and max IPG
determined according to a 16 bit LFSR.
The LFSR polynomial used is X^16 + X^10 + X^7 + X^1. Seed: 16'hFFFF
In order to get a constant rate, min IPG should be equal to max IPG.
Min IPG should always be smaller or equal to max IPG.
Field Bit(s)
Initial
Value
Description
DA 31:0 0h Packet Generator Source Address Low
The lower 32 bits of the 48-bit Ethernet destination address used for packets sent by
the packets generator.
Field Bit(s)
Initial
Value
Description
DA 15:0 0h Packet Generator Source Address High
The higher 16 bits of the 48-bit Ethernet destination address used for packets sent by
the packets generator.
Reserved 31:16 0h Reserved
Field Bit(s)
Initial
Value
Description
Min IPG 15:0 0h Minimum IPG
Minimum gap between packets sent by the packet generator.
Max IPG 31:16 0h Maximum IPG
Maximum gap between packets sent by the packet generator. Any configuration below
22 (20 if CRC is not added) results in the minimum IPG on the line.