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MAC Configuration Register Space — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 281
13.1.2 MAC Configuration Register Space
All device control/status registers detailed in Section 14.3, Main Register Descriptions, are implemented
per-LAN device. Each LAN device can be accessed using memory or I/O cycles, depending on the
specific BAR setting(s) established for that LAN device.
Register accesses to each MAC instance are independent. An outstanding read for one LAN device does
not impact the 82575’s ability to accept a register access to the other LAN. PCIe* bus operation, where
each register access results in a completion by one LAN device, in no way prevents the other LAN
device from accepting and servicing its register space as the 82575’s PCIe* core supports two credits
for memory accesses.
13.1.3 SDP, LED, INT# Output
Each LAN device provides an independent set of LED outputs and software-programmable I/O pins
(SDP). Four LED outputs and four SDP pins are provided per LAN device. These pins and their function
are bound to a specific LAN device (eight SDP pins cannot be associated with a single LAN device, for
example).
13.2 Shared EEPROM
The 82575 uses a single EEPROM device to configure hardware default parameters for both LAN
devices, including Ethernet Individual Addresses (IA), LED behaviors, receive packet-filters for
manageability and wakeup capability, etc. Certain EEPROM words are used to specify hardware
parameters which are LAN device-independent (such as those that affect circuits behavior). Other
EEPROM words are associated with a specific LAN device. LAN 0 and LAN 1 accesses the EEPROM to
obtain their respective configuration settings.
13.3 Shared FLASH
The 82575 provides an interface to an external FLASH/ROM memory device, as described in
Section 4.0. This FLASH/ROM device can be mapped into memory and/or I/O address space for each
LAN device through the use of PCI Base Address Registers (BARs). Bit 3 of the EEPROM Initialization
Control Word 3 associated with each LAN device selectively disables/enables whether the FLASH can be
mapped for each LAN device by controlling the BAR register advertisement and writeability.
13.3.1 FLASH Access Contention
The 82575 implements internal arbitration between Flash accesses initiated through the LAN "A" device
and those initiated through the LAN "B" device. If accesses from both LAN devices are initiated during
the same approximate size window, The first one is served first and only then the next one, Note that
the 82575 does not synchronize between the two entities accessing the Flash though contentions
caused from one entity reading and the other modifying the same locations is possible.