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Intel
®
82575EB Gigabit Ethernet Controller — Extended Device Control Register - CTRL_EXT
(00018h, R/W)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
308 January 2011
RO-DIS 17 0b Relaxed Ordering Disabled
When set to 1b, the 82575 does not request any relaxed ordering transactions
in PCIe* mode regardless of the state of bit 1 in the PCIe* command register.
When this bit is cleared and bit 1 of the PCIe* command register is set, the
82575 requests relaxed ordering transactions as provided by registers RXCTL
and TXCTL (per queue and per flow).
SerDes Low Power
Enable
18 0b
1
When set, allows the SerDes to enter a low power state when the function is
in Dr state as described in Section 7.4.1.1.
DMA Dynamic
Gating Enable
19 0b
1
When set, enables dynamic clock gating of the DMA and MAC units.
PHY Power Down
Enable
20 1b
1
When set, enables the PHY to enter a low-power state as described in
Section 7.4.0.3.
Reserved 21 0b Reserved. Should be set to 0b.
LINK_MODE 23:22 0b
1
Link Mode
This controls which interface is used to talk to the link.
00b = Direct copper (1000Base-T) interface (10/100/1000Base-T internal PHY
mode).
01b = Internal SerDes (legacy) interface.
10b = SGMII.
11b = Internal SerDes (new) interface.
EIAME 24 0b Extended Interrupt Auto Mask Enable
When set (usually in MSI-X mode), after sending an MSI-X message, bits set
in EIAM associated with this message are cleared. Otherwise, EIAM is used
only after a read or write of the EICR/EICS registers.
I2C Enabled 25 0b
1
Enable I2C
This bit enables the I
2
C bus that can be used to access SFP modules in the
EEPROM. If cleared, the I
2
C pads are isolated and accesses through I2CCMD
are ignored.
Extended VLAN 26 0b Extended VLAN
When set, all incoming Rx packets are expected to have at least one VLAN
with the Ether type as defined in VET.EXT_VET that should be ignored. The
packets can have a second VLAN that should be used for all filtering purposes.
All Tx packets are expected to have at least one VLAN added to them by the
host. In the case of an additional VLAN request (VLE) the second VLAN is
added after the VLAN is added by the host. This bit should only be reset only
by a PCIe* reset and should only be changed while Tx & Rx processes are
stopped.
Reserved 27 0b Reserved
Was IAME.
DRV_LOAD 28 0b Driver Loaded
This bit should be set by the driver after it loaded. This bit should be cleared
when the driver unloads or after a PCIe* soft reset. The MNG controller loads
this bit to indicate to the manageability controller that the driver has loaded.
Reserved 29 0b Reserved
Reads as 0b.
MEHE 30 0b Memory Error Handling Enable
When set, the 82575 reactions to uncorrectable memory error detection is
activated.
PBA_support 31 1b PBA Support
When set, setting one of the extended interrupts masks via EIMS causes the
PBA bit of the associated MSI-X vector to be cleared. Otherwise, the 82575
behaves in a way supporting legacy INT-x interrupts.
Should be cleared when working in INT-x or MSI mode and set in MSI-X mode.
Field Bit(s)
Initial
Value
Description