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Duplex Operation for Copper PHY Operation — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 243
Software can use MDIO accesses to read or write registers in either 1000Base-T or 10/100Base-T mode
by accessing the 82575’s MDIC register.
When working in SGMII/SerDes mode, the external PHY (if applicable) can be accessed either through
MDC/MDIO as previously described or via an I
2
C bus using the I2CCMD register. The I
2
C bus or the
MDC/MDIO bus are connected via the same pins, and are mutually exclusive. In order to be able to
control an external device, either by SFP or MDC/MDIO, the I
2
C SFP Enable bit in Initialization Control 3
EEPROM word should be set.
As the MDC/MDIO command can be targeted either to the internal PHY or to an external bus, the
MDIC.Destination bit is used to define the target of the transaction.
Note: Each port has its own MDC/MDIO or I
2
C bus and there is no sharing between the ports of
the control port. In order to control both port PHYs via the same control bus, accesses to
both PHYs should be done via the same port with different device addresses.
9.2 Duplex Operation for Copper PHY
Operation
The 82575 supports half-duplex and full-duplex 10/100 Mb/s MII mode either through internal copper
PHY or SGMII interface. However, only full-duplex mode is supported when SerDes mode is used or in
any 1000 Mb/s connection.
Configuration of the duplex operation of the 82575 can be forced or determined via the Auto-
Negotiation process. See Section 9.3 for details on link configuration setup and resolution.
9.2.1 Full Duplex
All aspects of the IEEE 802.3, 802.3u, 802.3z, and 802.3ab specifications are supported in full duplex
operation. Full duplex operation is enabled by several mechanisms depending on the speed
configuration of the 82575 and the specific capabilities of the PHY used in the application. During full
duplex operation, the 82575 can transmit and receive packets simultaneously across the link interface.
In full-duplex 10/100/1000Base-T mode, transmission and reception are delineated independently by
the 10/100/1000Base-T control signals. Transmission starts upon the assertion of TX_EN, which
indicates there is valid data on the TX_DATA bus driven from the MAC to the PHY. Reception is signaled
by the PHY by the assertion of the RX_DV signal which indicates valid receive data on the RX_DATA
lines to the MAC.
In SerDes mode, the transmission and reception of packets is indicated by symbols imbedded in the
data stream. These symbols delineate the packet encapsulation and the protocol does not rely on other
control signals.