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Interrupt Mask Clear Register - IMC (000D8h; W) — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 343
14.3.37 Interrupt Mask Clear Register - IMC (000D8h;
W)
Software uses this register to disable an interrupt. Interrupts are presented to the bus interface only
when the mask bit is set to 1b and the cause bit set to 1b. The status of the mask bit is reflected in the
Interrupt Mask Set/Read Register (see Section 14.3.36), and the status of the cause bit is reflected in
the Interrupt Cause Read Register (see Section 14.3.34). Reading this register returns the value of the
IMS register.
Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing a 1b
to the corresponding bit in this register. Bits written with 0b are unchanged (their mask status does not
change).
Field Bit(s)
Initial
Value
Description
TXDW 0 0b Sets/Reads the Transmit Descriptor Written Back Interrupt.
Reserved 1 - Reserved
LSC 2 0b Sets/Reads the Link Status Change Interrupt.
RXSEQ 3 0b Sets/Reads the Receive Sequence Error Interrupt.
RXDMT0 4 0b Sets/Reads the Receive Descriptor Minimum Threshold Hit Interrupt.
Reserved 5 0b Reserved.
RXO 6 0b Sets/Reads the Receiver Overrun Interrupt. Sets on Receive Data FIFO Overrun.
RXDW 7 0b Receiver Descriptor Write Back
Set when the 82575 writes back an Rx descriptor to memory.
Reserved 8 0b Reserved
Reads as 0b.
MDAC 9 0b Sets/Reads the MDIO/SFP Access Complete Interrupt.
RXCFG 10 0b Sets/Reads the Receiving /C/ Ordered Sets Interrupt.
GPI_SDP0 11 0b Sets/Reads the General Purpose Interrupt, related to SDP0 pin.
GPI_SDP1 12 0b Sets/Reads the General Purpose Interrupt, related to SDP1 pin.
GPI_SDP2 13 0b Sets/Reads the General Purpose Interrupt, related to SDP2 pin.
GPI_SDP3 14 0b Sets/Reads the General Purpose Interrupt, related to SDP3 pin.
Reserved 17:15 0b Reserved.
MNG 18 0b Sets/Reads the Management Event Interrupt.
Reserved 19 0b Reserved.
OMED 20 0b Sets/Reads the Other Media Energy Detected Interrupt.
Reserved 21 0b Reserved.
RX PBUR 22 0b Sets/Reads the Receive Packet Buffer Unrecoverable Error Interrupt.
TX PBUR 23 0b Sets/Reads the Transmit Packet Buffer Unrecoverable Error Interrupt.
RX DHER 24 0b Sets the Rx Descriptor Handler Error Interrupt.
TX DHER 25 0b Sets the Tx Descriptor Handler Error Interrupt.
SW WD 26 0b Sets the Software Watchdog Interrupt.
Reserved 27 0b Reserved.
OUTSYNC 28 0b Sets/Reads the DMA Tx Out of Sync Interrupt.
Reserved 31:29 0000b Reserved.