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Intel
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82575EB Gigabit Ethernet Controller — Power States
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
224 January 2011
On a transition from D3 to D0u, the 82575 PCI Configuration space is not reset. However, the 82575
requires that software perform a full re-initialization of the function including its PCI Configuration
Space.
7.4.1.3 D0 Active State
Once memory space is enabled, the 82575 enters an active state. It can transmit and receive packets if
properly configured by the driver. The PHY is enabled or re-enabled by the 82575 driver to operate/
auto-negotiate to full line speed/power if not already operating at full capability. Any APM Wakeup
previously active remains active. The driver can deactivate APM Wakeup by writing to the Wake Up
Control Register (WUC) or activate other Wake Up Filters by writing to the Wake Up Filter Control
Register (WUFC).
7.4.1.3.1 Entry to D0a State
D0a is entered from the D0u state by writing a 1b to the Memory Access Enable or the I/O Access
Enable bit of the PCI Command Register. The DMA, MAC, and PHY of the appropriate LAN function are
enabled.
7.4.1.4 D3 State
The D3 state referred to in this section is PCI PM D3hot.
The 82575 transitions to D3 when the system writes a 11b to the PowerState field of the Power
Management Control/Status register (PMCSR). Any WakeUp filter settings that were enabled before
entering this reset state are maintained. Upon transitioning to D3 state, the 82575 clears the Memory
Access Enable and I/O Access Enable bits of the PCI Command Register, which disables memory access
decode. In D3, the 82575 only responds to PCI configuration accesses and does not generate master
cycles.
Configuration and Message requests are the only TLPs accepted by a function in the D3hot state. All
other received Requests must be handled as Unsupported Requests and all received Completions can
optionally be handled as Unexpected Completions. If an error caused by a received TLP (for example,
an Unsupported Request) is detected while in D3hot, and reporting is enabled, the link must be
returned to L0 if it is not already in L0 and an error message must be sent.
A D3 state is followed by either a D0u state (in preparation for a D0a state) or by a transition to Dr
state (PCI PM D3cold state). To transition back to D0u, the system writes 00b to the Power State field of
the PMCSR. Transition to the Dr state is by asserting PE_RST_N.
7.4.1.4.1 Entry to D3 State
Transition to D3 state is through a configuration write to the Power State field of the PCI PM registers.
Prior to transition from D0 to the D3 state, the software device driver disables scheduling of further
tasks to the 82575. It masks all interrupts and does not write to the transmit descriptor tail register or
to the receive descriptor tail register and operates the master disable algorithm. If wake up capability is
needed, the software device driver should set up the appropriate wake up registers and the system
should write a 1b to the PME_En bit of the PMCSR or to the Auxiliary Power PM Enable bit of the PCIe*
Device Control Register before the transition to D3.