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Intel
®
82575EB Gigabit Ethernet Controller — Discard PAUSE Frames and Pass MAC Control
Frames
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
254 January 2011
Resumption of transmission can occur under the following conditions:
• Expiration of the PAUSE timer
• Reception of on XON frame (a frame with its PAUSE timer set to 0b)
Either condition clears the TXOFF status bit in the Device Status Register and transmission might
resume. Hardware records the number of received XON frames.
Note: When flow control reception is disabled (CTRL.RFCE = 0b), flow control packets are not
recognized and are parsed as regular packets.
9.3.5 Discard PAUSE Frames and Pass MAC Control
Frames
Two bits in the Receive Control register (RCTL) are implemented specifically for control over receipt of
PAUSE and MAC control frames. These bits are Discard PAUSE Frames (DPF) and Pass MAC Control
Frames (PMCF). See Section 14.3.47 for DPF and PMCF bit definitions.
The DPF bit forces the discarding of any valid PAUSE frame addressed to the 82575’s station address. If
the packet is a valid PAUSE frame and is addressed to the station address (receive address [0]), the
82575 does not pass the packet to host memory if the DPF bit is set to logic high. When DPF is cleared
to 0b, a valid flow control packet is transferred via DMA. This bit has no affect on PAUSE operation, only
the DMA function.
The PMCF bit allows for the passing of any valid MAC control frames to the system which do not have a
valid PAUSE opcode. In other words, the frame can have the correct MAC control frame multicast
address (or the MAC station address) as well as the correct type field match with the FCT register, but
does not have the defined PAUSE opcode of 0001h. Frames of this type are transferred to host memory
when PMCF is logic high.
9.3.6 Transmission of PAUSE Frames
Transmitting PAUSE frames is enabled by software writing a 1b to the CTRL.TFCE bit.
Similar to the reception flow control packets described earlier, XOFF packets can be transmitted only if
this configuration has been negotiated between the link partners via the Auto-Negotiation process. In
other words, the setting of this bit indicates the desired configuration.
The content of the Flow Control Receive Threshold High register determines at what point hardware
first transmits a PAUSE frame. Hardware monitors the fullness of the receive FIFO and compares it with
the contents of FCRTH. When the threshold is reached, hardware sends a PAUSE frame with its pause
time field equal to FCTTV.
At this time, hardware starts counting an internal shadow counter (reflecting the pause timeout counter
at the partner end) from zero. When the counter reaches the value indicated in FCRTV register, then, if
the PAUSE condition is still valid (meaning that the buffer fullness is still above the low watermark), an
XOFF message is sent again.
Once the receive buffer fullness reaches the low water mark, hardware sends an XON message (a
PAUSE frame with a timer value of 0). Software enables this capability with the XONE field of the
FCRTL.