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Packet Address Filtering — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 103
5.3.1 Packet Address Filtering
Hardware stores incoming packets in host memory subject to the following filter modes. If there is
insufficient space in the receive FIFO, hardware drops them and indicates the missed packet in the
appropriate statistics registers.
The following filter modes are supported:
• Exact Unicast/Multicast — The destination address must exactly match one of 16 stored
addresses. These addresses can be unicast or multicast.
Note: The software device driver can use only 15 entries (entries 0-14). Entry 15 should be kept
untouched by the software device driver. It can be used only by the manageability's
firmware or external TCO controller.
• Promiscuous Unicast — Receive all unicasts.
• Multicast — The upper bits of the incoming packet’s destination address index a bit vector that
indicates whether to accept the packet; if the bit in the vector is one, accept the packet, otherwise,
reject it. The controller provides a 4096 bit vector. Software provides four choices of which bits are
used for indexing. These are [47:36], [46:35], [45:34], or [43:32] of the internally stored
representation of the destination address.
• Promiscuous Multicast — Receive all multicast packets.
Note: When a promiscuous bit is set and a multicast packet is received, the PIF bit of the packet
status is not set.
• VLAN — Receive all VLAN packets that are for this station and have the appropriate bit set in the
VLAN filter table.
Normally, only good packets are received. These are defined as those packets with no CRC error,
symbol error, sequence error, length error, alignment error, or where carrier extension or RX_ERR errors
are detected. However, if the Store Bad Packet bit is set in the Receive Control register (RCTL.SBP),
then bad packets that pass the filter function are stored in host memory. Packet errors are indicated by
error bits in the receive descriptor (RDESC.ERRORS). It is possible to receive all packets, regardless of
whether they are bad, by setting the promiscuous enables and the Store Bad Packet bit.
Note: CRC errors before the SFD are ignored. Any packet must have a valid SFD in order to be
recognized by the 82575 (even bad packets).
The manageability engine might decide to snoop or redirect part of the received packets
according to external BMC instructions and EEPROM settings.
5.3.2 Receive Data Storage
The descriptor points to a memory buffer to store packet data. The size of the buffer can be set using
either the generic RCTL.BSIZE field, or the per queue SRRCTL[n].BSIZEPACKET field.
Receive buffer size, selected by bit settings in the Receive Control register (RCTL.BSIZE), support the
following buffer sizes:
• 256 B
• 512 B
• 1024 B
• 2048 B