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Interrupt Cause Set Register (ICS) — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 163
Note: When EICR is used in MSI-X mode, the Rx / Tx related bits in ICR should be masked.
5.13.2 Interrupt Cause Set Register (ICS)
This registers enables setting the bits of ICR by software, by writing a 1b in the corresponding bits in
ICS. Used to rearm interrupts software did not have time to handle in the current interrupt routine.
5.13.3 Interrupt Mask Set/Read Register (IMS)
An interrupt is enabled if its corresponding mask bit in this register is set to 1b and disabled if its
corresponding mask bit is set to 0b. A PCIe* interrupt is generated each time one of the bits in this
register is set and the corresponding interrupt condition occurs. The occurrence of an interrupt
condition is reflected by having a bit set in the ICR.
Reading this register returns which bits have an interrupt mask set.
A particular interrupt can be enabled by writing a 1b to the corresponding mask bit in this register. Any
bits written with a 0b are unchanged. Therefore, if software desires to disable a particular interrupt
condition that had been previously enabled, it must write to the IMC instead of writing a 0b to a bit in
this register.
5.13.4 Interrupt Mask Clear Register (IMC)
Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing a 1b
to the corresponding bit in this register. Bits written with 0b are unchanged (their mask status does not
change).
5.13.5 Interrupt Acknowledge Auto-mask register
(IAM)
An ICR read or write has the side effect of writing the contents of this register to the IMC register. If
CTRL_EXT.NSICR = 0b, then the copy of this register to IMS only occurs after at least one bit is set in
the IMS and there is a true interrupt as reflected in ICR.INTA.
5.13.6 Extended Interrupt Cause Registers (EICR)
This register records the non-error interrupts from the receive and transmit queues in a unique bit per
queue plus one bit to indicate when any interrupt in the ICR is active. Bits in this register can be
configured to auto-clear when the MSI-X interrupt message is sent in order to minimize software device
driver overhead when using MSI-X interrupt signaling.
In systems that do not support MSI-X, writing 1b's clears the corresponding bits in this register. Most
systems have write- buffering that minimizes overhead, but this might require a read operation to
guarantee that the write has been flushed from posted buffers. Reading this register auto-clears all
bits.