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Power States — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 225
As a response to being programmed into the D3 state, the 82575 brings its PCIe* link into the L1 link
state. As part of the transition into the L1 state, the 82575 suspends scheduling of new TLPs and waits
for the completion of all previous TLPs it has sent. The 82575 clears the Memory Access Enable and I/O
Access Enable bits of the PCI Command Register, which disables memory access decode. Any receive
packets that have not been transferred into system memory is kept in the 82575 and discarded later on
D3 exit. Any transmit packets that have not been sent can still be transmitted, assuming the Ethernet
link is valid.
To reduce power consumption, if APM wake or PCI PM PME is enabled, the PHY auto-negotiates to a
lower link speed on D3 entry.
7.4.1.4.2 Master Disable
System software can disable master accesses on the PCIe* link by either clearing the PCI Bus Master
bit or by bringing the function into a D3 state. From this point on, the 82575 must not issue master
accesses for this function. Due to the full duplex nature of PCIe* and the pipelined design in the 82575,
multiple requests from several functions might be pending when the master disable request arrives.
The protocol described in this section ensures that a function does not issue master requests to the
PCIe* link after its master enable bit is cleared or after entry to D3 state.
Two configuration bits are provided for the handshake between the 82575 function and its driver:
• GIO Master Disable bit in the Device Control Register (CTRL). When the GIO Master Disable bit is
set, the 82575 blocks new master requests, including manageability requests, by this function. The
82575 then proceeds to issue any pending requests by this function. This bit is cleared on master
reset (Internal_Power_On_Reset all the way to Software Reset) to allow master accesses.
• GIO Master Enable Status bits in the Device Status Register. These bits are cleared by the 82575
when the GIO Master Disable bit is set and no master requests are pending by the relevant
function. Otherwise, these bits are set. This indicates that no master requests is issued by this
function as long as the GIO Master Disable bit is set. The following activities must end before the
82575 clears the GIO Master Enable Status bit.
• Master requests by the transmit and receive engines
• Master requests by the manageability agents
• Reception of firmware indication that the interface to this function is Idle
• All pending completions to the 82575 are received
Note: The software device driver sets the GIO Master Disable bit when notified of a pending
master disable (or D3 entry). The 82575 then blocks new requests and proceeds to issue
any pending requests by this function. The driver then polls the GIO Master Enable Status
bit. Once the bit is cleared, it is guaranteed that no requests are pending from this function.
The driver might time-out if the GIO Master Enable Status bit is not cleared within a given
time.
The GIO Master Disable bit must be cleared to enable a master request to the PCIe* link.
This can be done either through reset or by the software device driver.
7.4.1.5 Link-Disconnect
In any of D0u, D0a, D3, or Dr, the 82575 enters a link-disconnect state if it detects a link-disconnect
condition on the Ethernet Link. Note that the link-disconnect state is invisible to software (other than
the Link Energy Detect bit state). In particular, while in D0 state, software might be able to access any
of the device registers as in a link-connect state.