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Intel
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82575EB Gigabit Ethernet Controller — Reset Operation
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
40 January 2011
a. SDP0_IODIR, SDP1_IODIR, SDP2_IODIR, SDP3_IODIR - reset on Internal_Power_On_Reset
only. Any EEPROM auto-load resets these fields to the values in the EEPROM.
b. Packet Buffer Allocation (PBA) - reset on Internal_Power_On_Reset only.
c. Packet Buffer Size (PBS) - reset on Internal_Power_On_Reset only.
d. LED configuration registers
e. The Aux Power Detected bit in the PCIe* Device Status register is reset on
Internal_Power_On_Reset and GIO Power Good only
f. FLA - reset on Internal_Power_On_Reset only.
5. The following registers are part of this group:
a. SWSM
b. GCR (only part of the bits; see Section 14.0)
c. FUNCTAG
d. GSCL_1/2/3/4
e. GSCN_0/1/2/3
f. SW_FW_SYNC (only part of the bits; see Section 14.0)
6. The Wake Up Context is defined in the PCI Bus Power Management Interface Specification (Sticky
bits). It includes:
a. PME_En bit of the Power Management Control/Status Register (PMCSR).
b. PME_Status bit of the Power Management Control/Status Register (PMCSR).
c. Aux_En in the PCIe* registers
d. The device Requester ID (since it is required for the PM_PME TLP).
e. The shadow copies of these bits in the Wakeup Control Register are treated identically.
7. Refers to bits in the Wake Up Control Register that are not part of the Wake-Up Context (the
PME_En and PME_Status bits).
8. The Wake Up Status Registers include the following:
a. Wake Up Status Register
b. Wake Up Packet Length.
c. Wake Up Packet Memory.
9. The manageability control registers refer to the following registers:
a. MANC - 5820h
b. MFUTP01-7 - 05030h - 504Ch
c. MFVAL - 05824h
d. MANC2H - 5860h
e. MAVTV1-7 - 0x5010 - 0x502C
f. MDEF0-7 - 890h - 58AC
g. MIPAF0-15 - 58B0h - 58ECh
10. MMAH/MMAL0-3 - 5910h - 592Ch
11. FWSM
Note: For detailed manageability control register information, refer to the Intel® 82575 TCO/
System Manageability Interface Application Note.
12. The Wake-up Management Registers include the following:
a. Wake Up Filter Control.