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EEPROM-Less Support — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 47
s32 is signed 32 bit value,
u8 is unsigned 8 bit value.
#define E1000_CCMCTL 0x05B48 /* CCM Control Register */
#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
#define E1000_SCCTL 0x05B4C /* PCIc PLL Cfg Register */
#define E1000_SCTL 0x00024 /* SerDes Control */
#define E1000_EECD 0x00010 /* EEPROM Control */
#define E1000_EECD_PRES 0x00000100 /* NVM Present */
#define E1000_GEN_CTL_READY 0x80000000
#define E1000_GEN_CTL_ADDRESS_SHIFT 8
#define E1000_GEN_POLL_TIMEOUT 640
Error codes are not required to be standard; programmers can define them as needed.
/* Is the EEPROM present? If not then run the tuning script*/
if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
if (hw->mac.type == e1000_82575) {
/* SerDes configuration via SERDESCTRL */
e1000_write_8bit_ctrl_reg(E1000_SCTL, 0x00, 0x0C);
e1000_write_8bit_ctrl_reg(E1000_SCTL, 0x01, 0x78);
e1000_write_8bit_ctrl_reg(E1000_SCTL, 0x1B, 0x23);
e1000_write_8bit_ctrl_reg(E1000_SCTL, 0x23, 0x15);
/* CCM configuration via CCMCTL register */
e1000_write_8bit_ctrl_reg(E1000_CCMCTL, 0x14, 0x00);
e1000_write_8bit_ctrl_reg(E1000_CCMCTL, 0x10, 0x00);
/* PCIe lanes configuration */
e1000_write_8bit_ctrl_reg(E1000_GIOCTL, 0x00, 0xEC);
e1000_write_8bit_ctrl_reg(E1000_GIOCTL, 0x61, 0xDF);
e1000_write_8bit_ctrl_reg(E1000_GIOCTL, 0x34, 0x05);