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Intel
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82575EB Gigabit Ethernet Controller — Transmit Descriptor Fetching
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
146 January 2011
address = base + (ptr * 16), where ptr is the value in the hardware head or tail register.
The size chosen for the head and tail registers permit a maximum of 64 K descriptors, or approximately
16 K packets for the transmit queue given an average of four descriptors per packet.
Once activated, hardware fetches the descriptor indicated by the hardware head register. The hardware
tail register points one beyond the last valid descriptor. Software reads the head register to determine
which packets-those logically before the head-have been transferred to the on-chip FIFO or
transmitted.
All the registers controlling the descriptor rings behavior should be set before transmit is enabled, apart
from the tail registers which are used during the regular flow of data.
Note: Software determines if a packet has been sent by either of three methods:
• Setting the RS bit in the transmit descriptor command field or by performing a PIO read of the
transmit head register or by reading the head value written by the 82575 to the address pointed by
the TDWBAL and TDWBAH register.
• Checking the transmit descriptor DD bit or head value in memory eliminates a potential race
condition. All descriptor data is written to the IO bus prior to incrementing the head register, but a
read of the head register could pass the data write in systems performing IO write buffering.
• Updates to transmit descriptors use the same IO write path and follow all data writes.
Consequently, they are not subject to the race.
In general, hardware prefetches packet data prior to transmission. Hardware typically updates the
value of the head pointer after storing data in the transmit FIFO.
5.7.1 Transmit Descriptor Fetching
The descriptor processing strategy for transmit descriptors is essentially the same as for receive
descriptors except that a different set of thresholds are used. As for receives, the number of on-chip
transmit descriptors has been increased (from 8 to 64), and the fetch and write-back algorithms
modified.
When the on-chip buffer is empty, a fetch happens as soon as any descriptors are made available (host
writes to the tail pointer). When the on-chip buffer is nearly empty (TXDCTL[n].PTHRESH), a prefetch is
performed each time enough valid descriptors (TXDCTL[n].HTHRESH) are available in host memory and
no other DMA activity of greater priority is pending (descriptor fetches and write-backs or packet data
transfers).
When the number of descriptors in host memory is greater than the available on-chip descriptor
storage, the chip may elect to perform a fetch which is not a multiple of cache line size. The hardware
performs this non-aligned fetch if doing so results in the next descriptor fetch being aligned on a cache
line boundary. This allows the descriptor fetch mechanism to be most efficient in the cases where it has
fallen behind software.
Note: The 82575 NEVER fetches descriptors beyond the descriptor tail pointer.
5.7.2 Transmit Descriptor Write-Back
The descriptor write-back policy for transmit descriptors is similar to that for receive descriptors with a
few additional factors. First, since transmit descriptor write-backs are optional (controlled by RS in the
transmit descriptor), only descriptors that have one (or both) of these bits set start the accumulation of