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Power States — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 223
• Pass through manageability is disabled
• ACPI PME is disabled for all PCI functions
• The 82575 Disable Power Down En EEPROM bit is set (default hardware value is disabled).
Entry into Dr Disable is usually done after asserting PE_RST_N. It can also be possible to enter Dr
Disable mode by reading the EEPROM while already in Dr state. The usage model for this later case is at
system power up, assuming that manageability and wake up are not required. Once the 82575 enters
Dr state on power-up, the EEPROM is read. If the EEPROM contents determines that the conditions to
enter Dr Disable are met, the 82575 then enters this mode (assuming that PE_RST_N is still asserted).
Exiting from Dr Disable is by de-asserting PE_RST_N.
7.4.1.1.2 Entry to Dr State
Dr entry on platform power up starts with the assertion of the internal power detection circuit
(Internal_Power_On_Reset). The EEPROM is read and determines the 82575 configuration. If the APM
Enable bit in the EEPROM Initialization Control Word 2 is set, then APM wake up is enabled. The MAC
and PHY state is determined by the manageability state and APM wake. To reduce power consumption,
if APM Wake is enabled, the PHY auto-negotiates to a lower link speed on Dr entry. The PCIe* link is not
enabled in Dr state following system power up (since PE_RST_N is asserted).
Entry to Dr state from D0a state is by asserting PE_RST_N. An ACPI transition to the G2/S5 state is
reflected in an 82575 transition from D0a to Dr state. The transition can be orderly (programmer
selects the shut down option), in which case the software device driver can have a chance to intervene.
Or, it might be an emergency transition (power button override), in which case, the software device
driver is not notified.
To reduce power consumption if any manageability, APM wake or PCI PM PME is enabled, the PHY auto-
negotiates to a lower link speed on D0a to Dr transition.
Transition from D3 state to Dr state is done by asserting PE_RST_N. Prior to that, the system initiates a
transition of the PCIe* link from L1 state to either the L2 or L3 state (assuming all functions were
already in D3 state). The link enters L2 state if PCI-PM PME is enabled.
7.4.1.2 D0 Uninitialized State
The D0u state is a low-power state used after PE_RST_N is de-asserted following power-up (cold or
warm), on hot reset (in-band reset through PCIe* physical layer message) or on D3 exit.
When entering D0u, the 82575 disables wake ups and asserts a reset to the PHY while the EEPROM is
being read. If the APM mode bit in the EEPROM Initialization Control Word 2 is set, then APM wake up is
enabled.
7.4.1.2.1 Entry to D0u State
D0u is reached from either the Dr state (de-asserting PE_RST_N) or the D3hot state (by configuration
software writing a value of 00b to the Power State field of the PCI PM registers).
De-asserting PE_RST_N means that the entire state of the 82575 is cleared except for the sticky bits.
The state is loaded from the EEPROM. Afterwards, the PCIe* link is established. When this completes,
the configuration software can access the 82575.