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Intel
®
82575EB Gigabit Ethernet Controller — PB Descriptor Read Pointers - PBDESCRP (02454h;
RO)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
434 January 2011
14.10.6 PB Descriptor Read Pointers - PBDESCRP
(02454h; RO)
14.10.7 Packet Buffer Diagnostic - PBDIAG (02458h; R/
W)
14.10.8 Transmit Data FIFO Head Register - TDFH
(03410h; RO)
This register stores the head of the on–chip transmit data FIFO. Since the internal FIFO is organized in
units of 64-bit words, this field contains the 64-bit offset of the current Transmit FIFO Head. A value of
8h in this register corresponds to an offset of 8 Qwords into the Transmit FIFO space. This register is
available for diagnostic purposes only, and should not be written during normal operation.
Field Bit(s)
Initial
Value
Description
rx_desc_rd_ptr 15:0 0h Rx descriptor read pointer value.
Reserved 31:16 0h Reserved.
Field Bit(s)
Initial
Value
Description
Rx_win_
threshold
11:0 600h Threshold in (qwords) of Rx FIFO for arbitration.
If the Rx FIFO has more data than this threshold then the Rx logic wins the arbitration
for writing a header to the header FIFO.
24 KB is the default.
Reserved 15:12 - Reserved.
Reserved 19:16 0010b Reserved.
DBU_empty
(RO)
20 - All FIFOs (Rx and Tx) are empty.
Cfg_rx_wait 21 0b Stop reading data from the receive data buffer to the DMA Rx machine. Diagnostic
only.
Cfg_tx_wait 22 0b Stop reading data from the transmit data buffer towards the Tx MAC. Diagnostic only
Far End
Loopback
23 0b Enable far end loopback at the packet buffer.
0b = Disable.
1b = Enable.
Reserved 25:24 00b Reserved
Always set to 00b.
Reserved 28:26 000b Reserved
Must be written with 000b.
STAT_SEL 31:29 0h
Field Bit(s)
Initial
Value
Description