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Intel
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82575EB Gigabit Ethernet Controller — Copper PHY Link Configuration
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
250 January 2011
There might be circumstances when the software device driver must forcibly set the link speed of the
MAC. This occurs when the link is manually configured. To force the MAC speed, the software device
driver must set the CTRL.FRCSPD (force-speed) bit to 1b and then write the speed bits in the Device
Control register (CTRL.SPEED) to the desired speed setting. See Section 14.3.1 for details.
Note: Forcing the MAC speed using CTRL.FRCSPD overrides all other mechanisms for configuring
the MAC speed and can yield non-functional links if the MAC and PHY are not operating at
the same speed/configuration.
When forcing the 82575 to a specific speed configuration, the software device driver must also ensure
the PHY is configured to a speed setting consistent with MAC speed settings. This implies that software
must access the PHY registers to either force the PHY speed or to read the PHY status register bits that
indicate link speed of the PHY.
Note: The forcing of the speed settings by CTRL.SPEED can also be accomplished by setting the
CTRL_EXT.SPD_BYPS bit. This bit bypasses the MAC’s internal clock switching logic and
gives the software device driver complete control over when the speed setting takes place.
The CTRL.FRCSPD bit uses the MAC’s internal clock switching logic which does delay the
affect of the speed change.
9.3.2.2.2 Using Internal PHY Direct Link-Speed Indication
The 82575’s internal PHY provides a direct internal indication of its speed to the MAC (SPD_IND). When
using the internal PHY, the most direct method for determining the PHY link speed and either manually
or automatically configuring the MAC speed is based on these direct speed indications.
For MAC speed to be set/determined from these direct internal indications from the PHY, the MAC must
be configured such that CTRL.ASDE and CTRL.FRCSPD are both 0b (both auto-speed detection and
forced-speed override disabled). With the CTRL register configured, the MAC speed is reconfigured
automatically each time the PHY indicates a new link-up event to the MAC.
When MAC speed is neither forced nor auto-sensed by the MAC, the current MAC speed setting and the
speed indicated by the PHY is reflected in the Device Status register bits STATUS.SPEED.
9.3.2.3 MAC Full/Half Duplex Resolution
The duplex configuration of the link is also resolved by the PHY during the Auto-Negotiation process.
The 82575’s internal PHY provides an internal indication to the MAC of the resolved duplex configuration
using an internal full-duplex indication (FDX).
When using the internal PHY, this internal duplex indication is normally sampled by the MAC each time
the PHY indicates the establishment of a good link (LINK indication). The PHY’s indicated duplex
configuration is applied in the MAC and reflected in the MAC Device Status register (STATUS.FD).
Software can override the duplex setting of the MAC via the CTRL.FD bit when the CTRL.FRCDPLX
(force duplex) bit is set. If CTRL.FRCDPLX is 0b, the CTRL.FD bit is ignored and the PHY’s internal
duplex indication applied.
9.3.2.4 Using PHY Registers
The software device driver might be required under some circumstances to read from, or write to, the
MII management registers in the PHY. These accesses are performed via the MDIC registers. The MII
registers enable the software device driver to have direct control over the PHY’s operation which might
include: