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Intel
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82575EB Gigabit Ethernet Controller — TCP Timer Interrupt
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
170 January 2011
5.16.1 TCP Timer Interrupt
In order to implement TCP timers for I/OAT 2, software needs to take action periodically (every 10
milliseconds). The software device driver must rely on software-based timers, whose granularity can
change from platform to platform. This software timer generates a software Network Interface Card
(NIC) interrupt, which then enables the software device driver to perform timer functions as part of its
usual DPC. Note that the timer interval is system-specific.
It would be more accurate and more efficient for this periodic timer to be implemented in hardware.
The software device driver could program a timeout value (usual value of 10 ms), and each time the
timer expires, hardware sets a specific bit in the EICR. When an interrupt occurs (due to normal
interrupt moderation schemes), software reads the EICR and discovers that it needs to process timer
events during that DPC.
The timeout should be programmable by the software device driver, and it should be able to disable the
timer interrupt if it is not needed.
A stand-alone down-counter is implemented. with an interrupt issued each time the value of the
counter is zero.
Software is responsible for setting the initial value for the timer in the Duration field. Kick-starting is
done by writing a 1b to the Kick Start bit.
Following kick-starting, an internal counter is set to the value defined by the Duration field. Afterwards,
the counter is decreased by one each millisecond. When the counter reaches zero, an interrupt is
issued. The counter re-starts counting from its initial value if the Loop field is set.
5.17 Memory Error Correction and Detection
The 82575 internal memories are protected by error correcting code that might correct memory errors
and detect uncorrectable error. Correctable errors are silently corrected and are counted in the
PBECCSTS.Corr_err_cnt, RDHESTS.Corr_err_cnt or TDHESTS.Corr_err_cnt fields according to the
memory in which the error was found.
Uncorrectable errors are counted in the PBECCSTS.Uncorr_err_cnt, RDHESTS.Uncorr_err_cnt or
TDHESTS.Uncorr_err_cnt fields according to the memory in which the error was found. The 82575
reacts to uncorrectable error detection according to the location in which the error was found:
• If the error was detected in a receive packet data, the packet is sent to the host with the RXE bit set
in the receive descriptor. This packet should be discarded by the host.
• If the error was detected in a transmit packet data, the packet is sent to the network with a wrong
FCS so that the link partner can discard it.
• If the error was detected in the descriptors attached to receive or transmit packets or in the
descriptor handler cache memory, the consistency of the receive/transmit flow cannot be
guaranteed. In this case, the flow in which the error was detected is stopped and an interrupt is
generated indicating the location of the detected error. The flow stop can be released only by a
software reset (CTRL.RST). The interrupt causes used to indicate an unrecoverable error are
ICR[25:22] according to the location of the error.
Enabling the reaction mechanism of the 82575 to uncorrectable errors is done using the
CTRL_EXT.MEHE bit.