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82575EB Gigabit Ethernet Controller — Interrupt Throttle - EITR (01680h + 4*n [n = 0..9];
R/W)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
348 January 2011
14.3.45 Interrupt Throttle - EITR (01680h + 4*n [n =
0..9]; R/W)
• Interrupt Throttle Register Queue 0 EITR0 (0x01680)
• Interrupt Throttle Register Queue 1 EITR1 (0x01684)
• Interrupt Throttle Register Queue 2 EITR2 (0x01688)
• Interrupt Throttle Register Queue 3 EITR3 (0x0168C)
• Interrupt Throttle Register Queue 4 EITR4 (0x01690)
• Interrupt Throttle Register Queue 5 EITR5 (0x01694)
• Interrupt Throttle Register Queue 6 EITR6 (0x01698)
• Interrupt Throttle Register Queue 7 EITR7 (0x0169C)
• Interrupt Throttle Register Queue 8 EITR8 (0x016A0)
• Interrupt Throttle Register Queue 9 EITR9 (0x016A4)
Each EITR is responsible for an interrupt cause. The allocation of EITR-to-interrupt cause is through
MSI-X allocation registers.
Software uses this register to pace (or even out) the delivery of interrupts to the host processor. This
register provides a guaranteed inter-interrupt delay between interrupts asserted by the 82575,
regardless of network traffic conditions. To independently validate configuration settings, software can
use the following algorithm to convert the inter-interrupt interval value to the common interrupts/sec
performance metric:
interrupts/sec = (256 10
-9
sec interval)
-1
For example, if the interval is programmed to 500d, the 82575 guarantees the processor will not be
interrupted by it for 128 s from the last interrupt. The maximum observable interrupt rate from the
82575 should never exceed 7813 interrupts/sec.
Inversely, inter-interrupt interval value can be calculated as:
inter-interrupt interval = (256 10
-9
sec interval)
-1
The optimal performance setting for this register is very system and configuration specific. An initial
suggested range is 65 to -5580 (28B - 15CC).
Note: When working at 10/100 Mb/s and running at ¼ clock, the interval time is doubled by four.
Setting EITR to a non zero value can cause an interrupt cause Rx/Tx statistics miscount.
Reserved 29:12 0h Reserved
TCP Timer 30 0b Auto mask bit for the corresponding EICR TCP timer interrupt condition.
Other Cause 31 1b Auto mask bit for the corresponding EICR other cause interrupt condition.
Field Bit(s)
Initial
Value
Description