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Transmit Descriptor Length - TDLEN (03808h + 100*n [n=0..3]; R/W) — Intel
®
82575EB Gigabit
Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 367
14.3.70 Transmit Descriptor Length - TDLEN (03808h +
100*n [n=0..3]; R/W)
These registers contain the descriptor length and must be 128-byte aligned.
• Queue0 - TDLEN0 (03808h)
• Queue1 - TDLEN1 (03908h)
• Queue2 - TDLEN2 (03A08h)
• Queue3 - TDLEN3 (03B08h)
14.3.71 Transmit Descriptor Head - TDH (03810h +
100*n [n=0..3]; R/W)
These registers contain the head pointer for the transmit descriptor ring. It points to a 16-byte datum.
Hardware controls this pointer.
Note: The values in these registers might point to descriptors that are still not in host memory. As
a result, the host cannot rely on these values in order to determine which descriptor to
release.
• Queue0 - TDH0 (03810h)
• Queue1 - TDH1 (03910h)
• Queue2 - TDH2 (03A10h)
• Queue3 - TDH3 (03B10h)
14.3.72 Transmit Descriptor Tail - TDT (03818h + 100*n
[n=0..3]; R/W)
These registers contain the tail pointer for the transmit descriptor ring and points to a 16-byte datum.
Software writes the tail pointer to add more descriptors to the transmit ready queue. Hardware
attempts to transmit all packets referenced by descriptors between head and tail.
• Queue0 - TDT0 (03818h)
Field Bit(s)
Initial
Value
Description
reserved 6:0 00h Ignore on writes.
Reads back as 00h.
LEN 19:7 0h Descriptor Length
Reserved 31:20 0h Reserved
Reads as 0b.
Should be written to 0b.
Field Bit(s)
Initial
Value
Description
TDH 15:0 0h Transmit Descriptor Head
Reserved 31:16 0h Reserved
Should be written to 0b.