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Intel
®
82575EB Gigabit Ethernet Controller — Hardware Accessed Words
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
68 January 2011
4.5.1.18 PCIe* Control (Word 1Bh)
This word configures initial settings for the PCIe* default functionality.
3:2 Active
State PM
Support
11b This field determines support for Active State Link Power Management. It is loaded into the
PCIe* Active State Link PM Support register.
00b = Reserved.
01b = L0s entry supported.
10b = Reserved.
11b = L0s and L1 supported.
1 Slot
Clock Cfg
1b When this bit is set, the 82575 uses the PCIe* reference clock supplied on the connector.
This is primarily used for add-in solutions.
0 Loopbac
k Polarity
Inversion
0b This field verifies the polarity inversion in loopback master entry.
Table 17. PCIe* Control (Word 1Bh)
Bit(s) Name Default Description
15 Reserved 0b Reserved.
14 Dummy
Function
Enable
0b Dummy Function Enable
0b = Disabled function 0 is replace with function 1.
1b = Disabled function 0 is replaced with dummy function.
13 GIO Down
Reset
Disable
0b This bit disables a core reset when the PCIe* link goes down.
0b = Enable.
1b = Disable.
12 Lane
Reversal
Disable
0b This bit disables the ability to negotiate lane reversal.
0b = Enable.
1b = Disable.
11 Good
Recovery
0b When set to 1b, the LTSSM Recovery states always progresses towards LinkUp (force a
good recovery, when a recovery occurs).
0b = Normal mode.
10 Reserved 1b Reserved. Should always be set to 1b.
0b - Enable.
1b = Disable.
9:7 Reserved 000b Reserved. Always set to 000b.
6 GIO TS
Retrain
Mode
0b This bit controls the condition of LTSSM entry to recovery.
0b = Normal mode.
1b = Special mode.
5 L2 Disable 0b This bit disables the link from entering L2 state.
0b = Enable.
1b = Disable.
4 Skip
Disable
0b This bit disables the SKIP symbol insertion in the elastic buffer.
0b = Enable.
1b = Disable.
Table 16. PCIe* Initialization Configuration 3 (Word 1Ah)
Bit(s) Name Default Description