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Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 951 of 982
REJ09B0023-0400
Trc Trc Trc Tmw TdeTr rTrrTpwTp Trc
tCSD1
tAD1
tAD1tAD1
PALL REF REF
MRS
tRWD1
tRWD1
tRWD1
tCSD1
tCSD1
tCSD1
tRASD1tRASD1
tRASD1
tRASD1
tAD1
tAD1
tCASD1
tCASD1
(Hi-Z)*
3
tCSD1
tCSD1
tRASD1
tRASD1
tCASD1
tCASD1
tCSD1
tCSD1
tRWD1
tRWD1
tRASD1
tRASD1
tCASD1
tCASD1
CKIO
A25 to A0
CSn
RD/WR
A12/A11*
1
D31 to D0
RASU/L
CASU/L
BS
CKE
DQMxx
DACKn*
2
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
3. Pins D31 to D16 with weak keeper are retained as weak keepers.
Figure 25.39 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)