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Section 23 I/O Ports
Rev. 4.00 Sep. 14, 2005 Page 845 of 982
REJ09B0023-0400
Table 23.1 Port A Data Register (PADR) Read/Write Operations
PAnMD2 PAnMD1 Pin Function Read Write
0 0 Input Pin state Data is written to PADR, but does not affect
pin state.
1 Output PADR value Data is written to PADR and the value is
output from the pin.
1 0 Reserved
1 Other functions Pin state Data is written to PADR, but does not affect
pin state.
(n = 0 to 14)
23.2 Port B
Port B is a 9-bit input/output port with the pin configuration shown in figure 23.2. Each pin is
controlled by the port B control register (PBCR) in the PFC.
PTB8 (input/output)/DPLS (input)
Port B
PTB7 (input/output)/DMNS (input)
PTB6 (input/output)/TXDPLS (output)
PTB5 (input/output)/TXDMNS (output)
PTB4 (input/output)/TXENL (output)
PTB3 (input/output)/XVDATA (input)
PTB2 (input/output)/SUSPND (output)
PTB1 (input/output)/VBUS (input)
PTB0 (input/output)/UCLK (input)
Figure 23.2 Port B
23.2.1 Register Description
Port B has the following register.
• Port B data register (PBDR)