Renesas HD6417641 Network Card User Manual


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Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 78 of 982
REJ09B0023-0400
System Control Instructions
Table 2.24 System Control Instructions
Instruction
Instruction Code
Operation
Execution
States
T Bit
CLRMAC 0000000000101000 0 MACH, MACL 1
CLRS 0000000001001000 0 S 1
CLRT 0000000000001000 0 T 1 0
LDC Rm,SR 0100mmmm00001110 Rm SR 6 LSB
LDC Rm,GBR 0100mmmm00011110 Rm GBR 4
LDC Rm,VBR 0100mmmm00101110 Rm VBR 4
LDC Rm,SSR 0100mmmm00111110 Rm SSR 4
LDC Rm,SPC 0100mmmm01001110 Rm SPC 4
LDC Rm,R0_BANK 0100mmmm10001110 Rm R0_BANK 4
LDC Rm,R1_BANK 0100mmmm10011110 Rm R1_BANK 4
LDC Rm,R2_BANK 0100mmmm10101110 Rm R2_BANK 4
LDC Rm,R3_BANK 0100mmmm10111110 Rm R3_BANK 4
LDC Rm,R4_BANK 0100mmmm11001110 Rm R4_BANK 4
LDC Rm,R5_BANK 0100mmmm11011110 Rm R5_BANK 1
LDC Rm,R6_BANK 0100mmmm11101110 Rm R6_BANK 4
LDC Rm,R7_BANK 0100mmmm11111110 Rm R7_BANK 4
LDC.L @Rm+,SR 0100mmmm00000111 (Rm) SR, Rm + 4 Rm 8 LSB
LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) GBR, Rm + 4 Rm 4
LDC.L @Rm+,VBR 0100mmmm00100111 (Rm) VBR, Rm + 4 Rm 4
LDC.L @Rm+,SSR 0100mmmm00110111 (Rm) SSR, Rm + 4 Rm 4
LDC.L @Rm+,SPC 0100mmmm01000111 (Rm) SPC, Rm + 4 Rm 4
LDC.L @Rm+,
R0_BANK
0100mmmm10000111 (Rm) R0_BANK,
Rm + 4 Rm
4 —
LDC.L @Rm+,
R1_BANK
0100mmmm10010111 (Rm) R1_BANK,
Rm + 4 Rm
4 —
LDC.L @Rm+,
R2_BANK
0100mmmm10100111 (Rm) R2_BANK,
Rm + 4 Rm
4 —
LDC.L @Rm+,
R3_BANK
0100mmmm10110111 (Rm) R3_BANK,
Rm + 4 Rm
4 —