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Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 530 of 982
REJ09B0023-0400
18.3.3 Timer I/O Control Register (TIOR)
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU
has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2.
Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is
valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM
mode 2, the output at the point at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Bit Bit Name
Initial
value R/W Description
7
6
5
4
IOB3
IOB2
IOB1
IOB0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control B3 to B0
Specify the function of TGRB.
See the following tables.
TIORH_0: Table 18.10
TIOR_1: Table 18.12
TIOR_2: Table 18.13
TIORH_3: Table 18.14
TIORH_4: Table 18.16
3
2
1
0
IOA3
IOA2
IOA1
IOA0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control A3 to A0
Specify the function of TGRA.
See the following tables.
TIORH_0: Table 18.18
TIOR_1: Table 18.20
TIOR_2: Table 18.21
TIORH_3: Table 18.22
TIORH_4: Table 18.24