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Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 687 of 982
REJ09B0023-0400
Module data bus
SCFRDR
(16 stage)
SCRSR
RxD
TxD
SCK
CTS
RTS
SCFTDR
(16 stage)
SCTSR
SCSMR
SCLSR
SCFDR
SCFCR
SCFSR
SCBRRn
Parity generation
Parity check
Transmission/
reception
control
Baud rate
generator
Clock
External clock
Pφ
Pφ/4
Pφ/16
Pφ/64
TXI
RXI
ERI
BRI
SCIF
Bus interface
Internal
data bus
SCSCR
SCSPTR
SCRSR:
SCFRDR:
SCTSR:
SCFTDR:
SCSMR:
SCSCR:
[Legend]
SCFSR:
SCBRR:
SCSPTR:
SCFCR:
SCFDR:
SCLSR:
Receive shift register
Receive FIFO data register
Transmit shift register
Transmit FIFO data register
Serial mode register
Serial control register
Serial status register
Bit rate register
Serial port register
FIFO control register
FIFO data count register
Line status register
Figure 19.1 Block Diagram of SCIF