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Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 442 of 982
REJ09B0023-0400
CKIO
CPU CPU DMAC
CKIO
CPU CPU DMAC
DMAC
1st acceptance
1st acceptance
Acceptance
start
Acceptance
start
Acceptance
start
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
Non sensitive period
Non sensitive period
2nd acceptance
2nd acceptance
3rd
acceptance
Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection
Figure 13.17 shows the TEND output timing.
CKIO
DACK
DREQ
TEND
Bus cycle
End of DMA transfer
DMAC CPU CPUCPU DMAC
Figure 13.17 Example of DREQ Input Detection in Burst Mode Level Detection