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Section 16 I
2
C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 494 of 982
REJ09B0023-0400
5. Clear TDRE.
TDRE
TEND
ICDRS
ICDRR
1
A
2134567899
A
TRS
ICDRT
SCL
(Master output)
Slave receive mode Slave transmit mode
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
Bit 7 Bit 7
Data 1
Data 1
Data 2 Data 3
Data 2
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3)
User
processing
Figure 16.9 Slave Transmit Mode Operation Timing (1)