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Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 410 of 982
REJ09B0023-0400
13.3.4 DMA Channel Control Registers (CHCR)
DMA channel control registers (CHCR) are 32-bit read/write registers that control the DMA
transfer mode. The CHCR is initialized to H'00000000 at reset and retains the current value in the
standby or module standby mode.
Bit Bit Name
Initial
Value R/W Descriptions
31 TC 0 R/W Transfer Count Mode
This bit selects whether it transmits once by one
transfer request or transmits the number of setting
times of DMATCR by one transfer request. This bit is
effective only when transfer request original is MTU0 to
MTU4, and CMT0 and CMT1 at an On-chip peripheral
module request. Other than this, please specify 0 to be
this bit then.
0: It transmits once by one transfer request.
1: It transmits the number of setting times of DMATCR
by one transfer request.
30 to 24 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
23 DO 0 R/W DMA Overrun
This bit selects whether DREQ is detected by overrun
0 or by overrun 1. This bit is valid only in CHCR_0 and
CHCR_1.This bit is always read as 0 in CHCR_1 and
CHCR_3. The write value should always be 0.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
22 TL 0 R/W Transfer End Level
This bit specifies the TEND signal output is high active
or low active. This bit is valid only in CHCR_0.This bit
is always read as 0 in CHCR_1 and CHCR_3. The
write value should always be 0.
0: Low-active output of TEND
1: High-active output of TEND