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Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 422 of 982
REJ09B0023-0400
• DMARS1
Bit Bit Name
Initial
Value R/W Description
15
14
13
12
11
10
C3MID5
C3MID4
C3MID3
C3MID2
C3MID1
C3MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request module ID for DMA channel 3 (MID).
See table 13.3.
9
8
C3RID1
C3RID0
0
0
R/W
R/W
Transfer request module ID for DMA channel 3 (RID).
See table 13.3.
7
6
5
4
3
2
C2MID5
C2MID4
C2MID3
C2MID2
C2MID1
C2MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request module ID for DMA channel 2 (MID).
See table 13.3.
1
0
C2RID1
C2RID0
0
0
R/W
R/W
Transfer request module ID for DMA channel 2 (RID).
See table 13.3.