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Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 631 of 982
REJ09B0023-0400
Compare
match buffer
signal
Compare
match signal
Write signal
Address
Pφ
Buffer register
address
Buffer register
TGR write cycle
T1
T2
M
TGR
N
M
Buffer register write data
Figure 18.74 Conflict between Buffer Register Write and Compare Match (Channel 0)
Pφ
Address
Write signal
Compare match
signal
Compare match
buffer signal
TGR write cycle
T1
T2
Buffer register
address
N
N
M
Buffer register write data
Buffer register
TGR
Figure 18.75 Conflict between Buffer Register Write and Compare Match
(Channels 3 and 4)