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Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 418 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
16 DME 0 R/W DMA Master Enable
DME enables or disables DMA transfers on all
channels. If the DME bit and the DE bit corresponding
to each channel in CHCR are set to 1s, transfer is
enabled in the corresponding channel. If this bit is
cleared during transfer, transfers in all the channels
can be terminated.
Even if the DME bit is set, transfer is not enabled if the
TE bit is 1 or the DE bit is 0 in CHCR, or the NMIF bit
is 1 in DMAOR.
0: Disable DMA transfers on all channels
1: Enable DMA transfers on all channels
15 to 6 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
5
4
3
2
RC0
RC1
RC2
RC3
0
0
0
0
R/W
R/W
R/W
R/W
Round Robin Cannel Select
RC3, RC2, RC1, and RC0 select the priority level
between channels when there are transfer requests for
multiple channels simultaneously.
0: The priority level of the CHn (n: 0 to 3) is fixed.
When all RC bits is 0, the priority level is:
CH0 > CH1 > CH2 > CH3, equals with fixed mode
(mdoe7).
1: The priority level of the CHn (n: 0 to 3) is determined
by the round-robin. When all RC bits are 1, the
priority level between channels equals with round-
robin mode (mode 5).
1, 0 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * Writing 0 is possible to clear the flag.
If DMA transfers are requested to multiple channels simultaneously, the DMAC performs
transfers according to the specified channel priority. The channel priority is determined by the
round-robin select bits (RC0, RC1, RC2, RC3) and priority mode bits (PR1 and PR0) of the
DMAOR register.