Filter
Top Products
Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 720 of 982
REJ09B0023-0400
19.3.12 Line Status Register (SCLSR)
The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can
be cleared to 0 only if it has first been read (after being set to 1). SCLSR is initialized to H'0000
by a power-on reset.
Bit Bit Name
Initial
value R/W Description
15 to 1 — All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 ORER 0 R/(W)* Overrun Error
Indicates the occurrence of an overrun error.
0: Receiving is in progress or has ended normally*
1
[Clearing conditions]
• ORER is cleared to 0 when the chip is a power-on
reset
• ORER is cleared to 0 when 0 is written after 1 is
read from ORER.
1: An overrun error has occurred*
2
[Setting condition]
• ORER is set to 1 when the next serial receiving is
finished while the receive FIFO is full of 16-byte
receive data.
Notes: 1. Clearing the RE bit to 0 in SCSCR does
not affect the ORER bit, which retains its
previous value.
2. The receive FIFO data register (SCFRDR)
hold the data before an overrun error is
occurred, and the next receive data is
extinguished. When ORER is set to 1,
SCIF cannot continue the next serial
receiving.
Note: * The only value that can be written is 0 to clear the flag.