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Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 408 of 982
REJ09B0023-0400
13.3 Register Descriptions
Register configuration is described below. See section 24, List of Registers, for the addresses of
these registers and the state of them in each processing status.
Channel 0:
• DMA source address register_0 (SAR_0)
• DMA destination address register_0 (DAR_0)
• DMA transfer count register_0 (DMATCR_0)
• DMA channel control register_0 (CHCR_0)
Channel 1:
• DMA source address register_1 (SAR_1)
• DMA destination address register_1 (DAR_1)
• DMA transfer count register_1 (DMATCR_1)
• DMA channel control register _1 (CHCR_1)
Channel 2:
• DMA source address register_2 (SAR_2)
• DMA destination address register_2 (DAR_2)
• DMA transfer count register_2 (DMATCR_2)
• DMA channel control register_2 (CHCR_2)
Channel 3:
• DMA source address register_3 (SAR_3)
• DMA destination address register_3 (DAR_3)
• DMA transfer count register_3 (DMATCR_3)
• DMA channel control register_3 (CHCR_3)
Common:
• DMA operation register (DMAOR)
• DMA extension resource selector 0 (DMARS0)
• DMA extension resource selector 1 (DMARS1)