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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 292 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
5 to 2 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
1
0
HW1
HW0
0
0
R/W
R/W
Delay Cycles from RD, WEn Negation to Address, CSn
Negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5AWCR
Bit Bit Name
Initial
Value R/W Description
31 to 19 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
18
17
16
WW2
WW1
WW0
0
0
0
R/W
R/W
R/W
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
read access wait cycles)
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.