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Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 680 of 982
REJ09B0023-0400
Bit Bit Name
Initial
value R/W Description
9 OCE 0 R/W Output Level Compare Enable
This bit enables the start of output level comparisons.
When setting this bit to 1, pay attention to the output
pin combinations shown in table 18.43, Mode
Transition Combinations. When 0 is output on both
pins, the OSF bit is set to 1 at the same time when
this bit is set, and output goes to high impedance.
Accordingly, bit 6 and bits 4 to 0 in the port E data
register (PEDR) are set to 1. For the MTU output
comparison, set the bit to 1 after setting the MTU's
output pins with the PFC. Set this bit only when using
pins as outputs.
When the OCE bit is set to 1, if OIE = 0 a high-
impedance request will not be issued even if OSF is
set to 1. Therefore, in order to have a high-impedance
request issued according to the result of the output
level comparison, the OIE bit must be set to 1. When
OCE = 1 and OIE = 1, an interrupt request will be
generated at the same time as the high-impedance
request: however, this interrupt can be masked by
means of an interrupt controller (INTC) setting.
0: Output level compare disabled
1: Output level compare enabled; makes an output
high impedance request when OSF = 1.
8 OIE 0 R/W Output Short Interrupt Enable
This bit makes interrupt requests when the OSF bit of
the OCSR is set.
0: Interrupt requests disabled
1: Interrupt request enabled
7 to 0 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * The write value should always be 0.