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Rev. 4.00 Sep. 14, 2005 Page xlvi of l
Table 12.10 Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (3)........................................................................... 344
Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (4)-1........................................................................ 345
Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (4)-2........................................................................ 346
Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (5)-1........................................................................ 347
Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (5)-2........................................................................ 348
Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (6)-1........................................................................ 349
Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (6)-2........................................................................ 350
Table 12.14 Relationship between Access Size and Number of Bursts................................351
Table 12.15 Access Address in SDRAM Mode Register Write ...........................................371
Table 12.16 Output Addresses when EMRS Command Is Issued........................................ 374
Table 12.17 Relationship between Bus Width, Access Size, and Number of Bursts............ 376
Table 12.18 Minimum Number of Idle Cycles between
CPU Access Cycles for the Normal Space Interface ........................................ 389
Table 12.19 Minimum Number of Idle Cycles between Access Cycles during
DMAC Dual Address Mode Transfer for the Normal Space Interface.............390
Table 12.20 Minimum Number of Idle Cycles during DMAC Single Address Mode
Transfer to the Normal Space Interface from the
External Device with DACK ............................................................................ 391
Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and
the DMAC Dual Address Mode for the SDRAM Interface..............................393
Table 12.22 Minimum Number of Idle Cycles between Access Cycles of
the DMAC Single Address Mode for the SDRAM Interface ........................... 396
Section 13 Direct Memory Access Controller (DMAC)
Table 13.1
Pin Configuration.................................................................................................. 407
Table 13.2 Combination of the Round-Robin Select Bits and Priority Mode Bits .................420
Table 13.3 Transfer Request Module/Register ID.................................................................. 423
Table 13.4 Selecting External Request Modes with the RS Bits ............................................ 426
Table 13.5 Selecting External Request Detection with Dl, DS Bits ....................................... 427
Table 13.6 Selecting External Request Detection with DO Bit ..............................................427
Table 13.7 Selecting On-Chip Peripheral Module Request Modes with
the RS3 to RS0 Bits .............................................................................................. 428
Table 13.8 Supported DMA Transfers.................................................................................... 432
Table 13.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category ..... 439