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Section 3 DSP Operation
Rev. 4.00 Sep. 14, 2005 Page 105 of 982
REJ09B0023-0400
In ALU integer arithmetic operations, the lower word of the source operand is ignored and the
lower word of the destination operand is automatically cleared. The guard-bit parts are effective in
integer arithmetic operations if they are supported. Others are basically the same operation as
ALU fixed-point arithmetic operations. As shown in table 3.3, however, this type of operation
provides two kinds of instructions only, so that the second operand is actually either +1 or –1.
When a word data is loaded into one of the DSP unit's registers, it is input as an upper word data.
When a register providing guard bits is specified as an operand, the guard bits are also activated.
These operations, as well as fixed-point operations, are executed in the DSP stage, as shown in
figure 3.2. The DSP stage is the same stage as the MA stage in which memory access is
performed.
Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. This is the same as fixed-point
operations but the lower word of each source and destination operand is not used in order to
generate them. See section 3.1.1, ALU Fixed-Point Operations, for details.
In case of a conditional operation, they are not updated even though the specified condition is true
and the operation is executed. In case of an unconditional operation, they are always updated in
accordance with the operation result. See section 3.1.1, ALU Fixed-Point Operations, for details.
Overflow Protection: The S bit in SR is effective for any ALU integer arithmetic operations in
DSP unit. See section 3.1.8, Overflow Protection, for details.
3.1.3 ALU Logical Operations
Figure 3.7 shows the ALU logical operation flow. Table 3.4 shows the variation of this type of
operation. The correspondence between each operand and registers is the same as the ALU fixed-
point operations as shown in table 3.2.
Logical operations are also executed between registers. Each source and destination operand are
selected independently from one of the DSP registers. As shown in figure 3.7, this type of
operation uses only the upper word of each operand. The lower word and guard-bit parts are
ignored for the source operand and those of the destination operand are automatically cleared.
These operations are also executed in the DSP stage, as shown in figure 3.2. The DSP stage is the
same stage as the MA stage in which memory access is performed.