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Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 423 of 982
REJ09B0023-0400
Transfer requests from the various modules are specified by the MID and RID as shown in table
13.3.
Table 13.3 Transfer Request Module/Register ID
Peripheral Module
Setting Value for One
Channel (MID + RID)
MID
RID
Function
SCIF0 H'88 B'100010 B'00 Transmit
H'89 B'01 Receive
SCIF1 H'90 B'100100 B'00 Transmit
H'91 B'01 Receive
SCIF2 H'40 B'010000 B'00 Transmit
H'41 B'01 Receive
MTU0 H'A8 B'101010 B'00 TGI0A
MTU1 H'C0 B'110000 B'00 TGI1A
MTU2 H'C8 B'110010 B'00 TGI2A
MTU3 H'D0 B'110100 B'00 TGI3A
MTU4 H'E8 B'111010 B'00 TGI4A
USB H'A0 B'101000 B'00 Transmit
H'A1 B'01 Receive
A/D converter 1 H'B0 B'101100 B'00
CMT1 H'F0 B'111100 B'00
When MID/RID other than the values listed in table 13.3 is set, the operation of this LSI is not
guaranteed. The transfer request from the DMARS register is valid only when the resource select
bits (RS3 to RS0) have been set to B'1000 for CHCR0 to CHCR3 registers. Otherwise, even if the
DMARS has been set, transfer request source is not accepted.