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Section 20 USB Function Module
Rev. 4.00 Sep. 14, 2005 Page 794 of 982
REJ09B0023-0400
20.10 Notes on Usage
20.10.1 Receiving Setup Data
Note that the following when 8-byte setup data is received by USBEPDR0s.
1. The USB must always receive the setup command. Therefore, writing from the USB bus has
priority over reading from the CPU. When the USB starts receiving the next setup command
while the CPU is reading data after data reception, the USB forcibly invalidates reading from
the CPU to start writing. The value that is read after starting reception is undefined.
2. USBEPDR0s must be read in 8-byte unit. When reading is stopped in the middle, the data that
is received by the next setup command cannot be read correctly.
20.10.2 Clearing FIFO
If the connected USB cable is disconnected during communication, the data being received or
transmitted may remain in the FIFO. Therefore, clear the FIFO immediately after connecting the
USB cable.
Do not clear the FIFO that is receiving or transmitting data from or to the host.
20.10.3 Overreading or Overwriting Data Register
Note that the following when reading or writing the data register of this module:
Receive Data Register: Do not read the number of data which exceeds that of valid receive data
from the receive data register, i.e., data that exceeds the number of bytes indicated by the receive
data size register must not be read. For USBEPDR1 that has two FIFOs, the maximum number of
bytes that can be read at once is 64 bytes. After reading the data on the currently selected side,
write 1 to USBTRG/EP1RDFN to change the current side to another side. This allows the number
of bytes for the new side to be used as the receive data size, enabling the next data to be read.
Transmit Data Register: Do not write the number of data that exceeds the maximum packet size
to the transmit data register. For USBEPDR2 that has two FIFOs, the data to be written at one
time must be the maximum packet size or less. After writing the data, write 1 to TRG/PKTE to
change the currently selected side to another in the module to allow the next data to be written to
the new side. Therefore, do not write data to one side of FIFO right after the other side.