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Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 946 of 982
REJ09B0023-0400
CKIO
A25 to A0
CSn
RD/WR
A12/A11*
1
D31 to D0
RASU/L
CASU/L
BS
CKE
DQMxx
DACKn*
2
Note:
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Tc2 Tc3 Tc4Tr Tc1
t
AD1
t
CSD1
t
AD1
t
AD1
t
AD1
t
AD1
t
AD1
t
RWD1
t
RWD1
t
RWD1
t
CSD1
t
AD1
t
AD1
t
AD1
t
RASD1
t
RASD1
Row
address
Write command
Column
address
t
CASD1
t
CASD1
t
BSD
t
BSD
(High)
t
DQMD1
t
DQMD1
t
DACD
t
DACD
t
WDH2
t
WDD2
t
WDH2
t
WDD2
Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle, TRWL = 0 Cycle)