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Section 3 DSP Operation
Rev. 4.00 Sep. 14, 2005 Page 108 of 982
REJ09B0023-0400
Table 3.5 Variation of Fixed-Point Multiply Operation
Mnemonic Function Source 1 Source 2 Destination
PMULS Signed multiplication Se Sf Dg
Table 3.6 Correspondence between Operands and Registers
Register Se Sf Dg
A0 Yes
A1 Yes Yes Yes
M0 Yes
M1 Yes
X0 Yes Yes
X1 Yes —
Y0 Yes Yes
Y1 Yes
Note: The multiply operations basically generate 32-bit operation results. So when a register
providing the guard-bit parts are specified as a destination operand, the guard-bit parts will
copy bit 31 of the operation result.
The multiply operation of the DSP unit side is not integer but fixed-point arithmetic. So, the upper
words of each multiplier and multiplicand are input into a MAC unit as shown in figure 3.8. In the
SH's standard multiply operations, the lower words of both source operands are input into a MAC
unit. The operation result is also different from the SH's case. The SH's multiply operation result is
aligned to the LSB of the destination, but the fixed-point multiply operation result is aligned to the
MSB, so that the LSB of the fixed-point multiply operation result is always 0.
This fixed-point multiply operation is executed in one cycle Multiply operation is always
unconditional, but does not affect any condition code bits, DC, N, Z, V and GT, in DSR.
Overflow Protection: The S bit in SR is effective for this multiply operation in the DSP unit. See
section 3.1.8, Overflow Protection, for details.
If the S bit is 0, overflow occurs only when H'8000*H'8000 ((-1.0)*(-1.0)) operation is
executed as signed fixed-point multiply. The result is H'00 8000 0000 but it does not mean
(+1.0). If the S bit is 1, overflow is prevented and the result is H'00 7FFF FFFF.